RECONFIGURABLE PARRALEL MULTIPLE IN THE GALUIS FIELDS IN COMBINATION LOGIC
Timur A. Zubov, Vitaly V. Sukhotin, Anton V. Khnykin, Andrey V. Mishurov, Alexander A. Gorchakovsky
Abstract
The concept of «multiplier» in Galois fields, which are widely used in cryptography and noise-resistant coding, is considered. The architecture of a parallel multiplier for the Galois fields is analyzed. Reconfigurable multiplier is constructed. It is shown that the use of this type of multiplier will significantly reduce the number of logic gates.